1. Field of the Invention
The present invention relates to a semiconductor integrated circuit device.
2. Related Background Art
For years, 1T-1C (1 transistor 1 capacitor) DRAM (dynamic random access memory) devices have been manufactured. 1T-1C DRAMs having memory cells reduced in design rule to smaller than 0.1 μm are difficult to manufacture.
On this account, a DRAM having FBCs (floating body cells) as shown in FIG. 12 has been proposed (Japanese Patent Laid-open Publication No. JP2002-246571). FBC comprises a FET (field effect transistor) formed in SOI. The gate G of the FET is connected to a word line WL, the drain D is connected to b bit line BL, and the source S is connected to GND. The floating body FB functions as the data storage node.
FBC changes the number of carriers stored in the floating body FB and thereby changes the potential of the floating body FB. Data is stored by a change of threshold voltage of FET caused by the body effect.
For writing data “1” in FBC, both the word line WL and the bit line BL are raised to high potentials to bias FET toward the saturated state. Thereby, impact ionization is induced, and holes are stored in the floating body FB. The state with a larger number of holes stored in the floating body FB is regarded as data “1”.
For writing data “0” in FBC, the bit line BL is lowered to a negative potential, and the pn junction between the p-type body and the n-type body is thereby biased in the forward direction. As a result, the holes heretofore stored in the floating body FE are released to the bit line BL.
FIG. 13 is a cross-sectional view of another DRAM having FBCs (see “A Capacitorless Double-Gate DRAM Cell Design for High Density Applications” by C. Kuo, Tsu-Jae King and Chenming Hu, IEDM Tech. Digest, pp. 843-846, December 2002). This DRAM includes back gate electrodes BG in addition to front gate electrodes FG.
For writing data “0” in a floating body FE of this DRAM, both the floating gate electrode FG and the back gate electrode BG are set to high potentials whereas the potential barrier between the floating body FB and the source S is lowered. As a result, the holes heretofore stored in the floating body FE are released to the source S.
According to the DRAM shown in FIG. 12, the bit line BL is lowered to a negative potential to write data “0” in a selected cell, data of a non-selected cell connected to the same bit line BL and storing data “1” may be undesirably erased. This is generally called “0” disturbance.
In order to prevent “0” disturbance, the junction between the potential of the floating body FD of the non-selected cell and its drain D must be held in the reverse-biased or a weakly forward-biased condition (0.7 V or less). Therefore, it is necessary to lower the potential of the floating body FD of the non-selected cell to a sufficiently low negative potential by lowering the word line WL of the non-selected cell to an amply low negative potential.
According to the DRAM shown in FIG. 13, since the front gate electrode FG and the back gate electrode BG are parallel to each other, all cells connected to the activated word line WL are undesirably rewritten to data “0”. Therefore, upon refreshing operation and writing operation, the sense amplifier latches data of all cells connected to the word line WL before “0” is written (S1). After that, data “0” is once written in all cells (S2), and data “1” is rewritten only in those cells, having stored “1” just before “0” is written, according to the data latched in the sense amplifier (S3). Thus, the DRAM of this type needs steps S1 through S3. Therefore, the DRAM shown in FIG. 13 needs a long cycle time for the refreshing and writing operations and needs sense amplifier circuits for individual bit lines BL.
The DRAM including sense amplifier circuits for individual bit line BL decreases the cell efficiency and increases in chip size because the sense amplifier circuits occupy a large area. This means that FBC will lose its advantage of having a smaller cell size than 1T-1C type DRAM.
It is therefore desired to provide a semiconductor integrated circuit device reduced in refreshing cycle time and writing cycle time and reduced in chip size without influences of “0” disturbance.